JDP2S01T Datasheet, PDF (97/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 69: HcµPInterrupt register: bit description…continued
Bit
Symbol Description
2
ISTL_1_ 0 — no event
INT
1 — The transaction of the last PTD stored on the ISTL1 buffer has
been completed. The microprocessor is required to read data from
the ISTL1 buffer. The HCD must first read the HcBufferStatus
register to check the status of the ISTL1 buffer before reading data
to the microprocessor.
1
ISTL_0_ 0 — no event
INT
1 — The transaction of the last PTD stored on the ISTL0 buffer has
been completed. The microprocessor is required to read data from
the ISTL0 buffer. The HCD must first read the HcBufferStatus
register to check the status of the ISTL0 buffer before reading data
to the microprocessor.
0
SOF_INT 0 — no event
1 — The HC is in the SOF state and it indicates the start of a new
frame. The HCD must first read the HcBufferStatus register to
check the status of the ISTL buffer before reading data to the
microprocessor. For the microprocessor to perform the DMA
transfer of ISO data from or to the ISTL buffer, the HC must first
initialize the HcDMAConfiguration register.
15.4.5 HcµPInterruptEnable register (R/W: 25H/A5H)
The bits 9:0 in this register are the same as those in the HcµPInterrupt register. The
bits in this register are used together with bit 0 of the HcHardwareConfiguration
register to enable or disable the bits in the HcµPInterrupt register.
At power-on, all the bits in this register are masked with logic 0. This means no
interrupt request output on the interrupt pin INT1 can be generated. When a bit is set
to logic 1, the interrupt for that bit is enabled.
The bit allocation of the register is given in Table 70.
Code (Hex): 25 — read
Code (Hex): A5 — write
Table 70:
Bit
Symbol
HcµPInterruptEnable register: bit allocation
15
14
13
12
reserved
Reset
Access
Bit
Symbol
Reset
Access
-
-
7
INTL_IRQ_
Interrupt
Enable
0
R/W
-
-
6
ClkReady
0
R/W
-
-
5
HC
Suspended
Enable
0
R/W
-
-
4
OPR
Interrupt
Enable
0
R/W
11
-
-
3
EOT
Interrupt
Enable
0
R/W
10
-
-
2
ISTL_1
Interrupt
Enable
0
R/W
9
OTG_IRQ_
Interrupt
Enable
0
R/W
1
ISTL_0
Interrupt
Enable
0
R/W
8
ATL_IRQ_
Interrupt
Enable
0
R/W
0
SOF
Interrupt
Enable
0
R/W
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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