JDP2S01T Datasheet, PDF (19/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Control OUT (64 bytes)
Control IN (64 bytes)
Endpoint 1 (128 bytes)
Endpoint 2 (128 bytes)
Endpoint 3 (512 bytes)
Endpoint 4 (64 bytes)
Endpoint 5 (64 bytes)
Endpoint 6 (96 bytes)
Endpoint 7 (96 bytes)
004aaa057
Fig 7. DC buffer memory organization.
The buffer memory is configured by the DcEndpointConfiguration registers (ECRs).
Although the control endpoint has a fixed configuration, all 16 endpoints (control OUT,
control IN and 14 programmable endpoints) must be configured before the DC
internally allocates the buffer. The 14 programmable endpoints could be programmed
into sizes ranging from 16 bytes to 1023 bytes, single or double buffering.
The DC buffer memory for each endpoint can be accessed through the
DcReadEndpointBuffer and DcWriteEndpointBuffer registers.
9.2 PIO access mode
The ISP1362 provides the PIO mode for external microprocessors to access its
internal control registers and buffer memory. It occupies only four I/O ports or four
memory locations of a microprocessor. An external microprocessor can read or write
to the internal control registers and buffer memory of the ISP1362 through the PIO
operating mode. Figure 8 shows the PIO interface between a microprocessor and the
ISP1362.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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