JDP2S01T Datasheet, PDF (76/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 43: HcInterruptEnable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
reserved
Reset
0
-
-
-
-
-
-
-
Access
R/W
-
-
-
-
-
-
-
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
-
0
0
0
0
0
-
0
Access
-
R/W
R/W
R/W
R/W
R/W
-
R/W
9397 750 12337
Product data
Table 44: HcInterruptEnable register: bit description
Bit
Symbol Description
31
MIE
MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — enable interrupt generation because of Root Hub Status
Change
5
FNO
0 — ignore
1 — enable interrupt generation because of Frame Number
Overflow
4
UE
0 — ignore
1 — enable interrupt generation because of Unrecoverable Error
3
RD
0 — ignore
1 — enable interrupt generation because of Resume Detect
2
SF
0 — ignore
1 — enable interrupt generation because of Start of Frame
1
-
reserved
0
SO
0 — ignore
1 — enable interrupt generation because of Scheduling Overrun
15.1.6 HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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