JDP2S01T Datasheet, PDF (141/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
20.2.5 DC single-cycle DMA write timing in DACK-only mode
Table 157: Dynamic characteristics: DC single-cycle DMA write timing in DACK-only mode
Symbol
Parameter
Conditions
Min
Typ
t_ASRP
DREQ2 off after DACK2 on
-
-
t_ASAP
DACK2 pulse width
t_ASAP + t_APRS DREQ2 on after DACK2 off
25
-
180
-
t_ASDV
data valid after DACK2 on
-
-
t_APDZ
data hold after DACK2 off
-
-
Max
40
-
-
22
3
Unit
ns
ns
ns
ns
ns
DREQ2
DACK2⁽¹⁾
t _ASAP
t _ASRP
t _APRS
t _ASDV
t _APDZ
DATA
(1) Programmable polarity: shown as active LOW.
Fig 37. DC single-cycle DMA write timing in DACK-only mode.
20.2.6 DC burst mode DMA timing
Table 158: Dynamic characteristics: DC burst mode DMA timing
Symbol Parameter
Conditions
Min
Typ
t_RSIH
input RD/WR HIGH after DREQ on
22
-
t_ILRP
DREQ off after input RD/WR LOW
-
-
t_IHAP
DACK off after input RD/WR HIGH
0
-
t_IHIL
DMA burst repeat interval (input t_RL or t_WL is 30 ns (min) 160
-
RD/WR HIGH to LOW)
004aaa113
Max
Unit
-
ns
-
ns
60
ns
-
ns
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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