JDP2S01T Datasheet, PDF (80/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 50:
Bit
31
30 to 14
13 to 0
HcFmRemaining register: bit description
Symbol Description
FRT
FrameRemainingToggle: This bit is loaded from the
FrameIntervalToggle (FIT) field of HcFmInterval whenever
FrameRemaining (FR) reaches 0. This bit is used by the HCD for
synchronization between FrameInterval (FI) and FrameRemaining
(FR).
-
reserved
FR[13:0]
FrameRemaining: This counter is decremented at each bit time.
When it reaches zero, it is reset by loading the FrameInterval (FI)
value specified in HcFmInterval at the next bit time boundary.
When entering the USBOperational state, the HC reloads it with
the content of the FrameInterval (FI) part of the HcFmInterval
register and uses the updated value from the next SOF.
15.2.3 HcFmNumber register (R/W: 0FH/8FH)
The HcFmNumber register is a 16-bit counter, and the bit allocation is given in
Table 51. It provides a timing reference for events happening in the HC and the HCD.
The HCD may use the 16-bit value specified in this register and generate a 32-bit
frame number without requiring frequent access to the register.
Code (Hex): 0F — read
Code (Hex): 8F — write
Table 51: HCFmNumber register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
15
14
13
12
11
10
9
8
Symbol
FN[15:8]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
FN[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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