JDP2S01T Datasheet, PDF (136/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
CS
A0
RD
D [15:0]
t _SHSL
t _RLRH
t _RHRL
t _SLRL
T _RC
t _SLWL
t _RHSH
t _WHSH
t _RLDV
t _RHDZ
tAS
tAH
data
valid
t _WL
data
valid
t _WHWL
TWC
data
valid
data
valid
WR
D [15:0]
data
valid
Fig 30. HC Programmed interface timing.
data
valid
t _WDH
data
valid
t _WDSU
data
valid
data
valid
MGT969
20.1.2 DC Programmed I/O timing
Table 152: Dynamic characteristics: DC Programmed interface timing
Symbol
Parameter
Conditions
Min
Read timing (see Figure 31)
t_RHAX
address hold time after RD HIGH
3
t_AVRL
address set-up time before RD LOW
0
t_SHDZ
data outputs high-impedance time after
-
CS HIGH
t_RHSH
chip deselect time after RD HIGH
0
t_RLRH
RD pulse width
25
t_RLDV
data valid time after RD LOW
-
t_SHRL + t_RLRH + t_RHSH read cycle time
180
Write timing (see Figure 32)
t_WHAX
t_AVWL
t_SHWL + t_WLWH + t_WHSH
t_WLWH
t_WHSH
t_DVWH
t_WHDZ
address hold time after WR HIGH
address set-up time before WR LOW
write cycle time
WR pulse width
chip deselect time after WR HIGH
data set-up time before WR HIGH
data hold time after WR HIGH
3
0
[1] ₁₈₀
22
0
5
3
Typ Max Unit
-
-
ns
-
-
ns
-
3
ns
-
-
ns
-
-
ns
-
22
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
[1] In the command to data phase, the minimum value of the write command to the read data or write data cycle time should be 205 ns.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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