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JDP2S01T Datasheet, PDF (113/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications | |||
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Philips Semiconductors
ISP1362
Single-chip USB OTG controller
16.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to conï¬gure and enable the embedded
endpoints. They also serve to set the USB assigned address of the DC and to
perform a device reset.
16.1.1 DcEndpointConï¬guration register (R/W: 30Hâ3FH/20Hâ2FH)
This command is used to access the DcEndpointConï¬guration register (ECR) of the
target endpoint. It deï¬nes the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), buffer memory size and buffering scheme. It also enables the endpoint
buffer memory. The register bit allocation is shown in Table 108. A bus reset will
disable all endpoints.
The allocation of buffer memory only takes place after all 16 endpoints have been
conï¬gured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have ï¬xed conï¬gurations, they must be included in the initialization
sequence and must be conï¬gured with their default values (see Table 14). Automatic
buffer memory allocation starts when endpoint 14 has been conï¬gured.
Remark: If any change is made to an endpoint conï¬guration that affects the allocated
memory (size, enable/disable), the buffer memory contents of all endpoints becomes
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the conï¬guration.
Code (Hex): 20 to 2F â write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F â read (control OUT, control IN, endpoint 1 to 14)
Transaction â write or read 1 byte (code or data)
Table 108: DcEndpointConï¬guration register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOEN
EPDIR
DBLBUF FFOISO
FFOSZ[3:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 109: DcEndpointConï¬guration register: bit description
Bit
Symbol
Description
7
FIFOEN
Logic 1 indicates an enabled buffer memory with allocated
memory. Logic 0 indicates a disabled buffer memory (no bytes
allocated).
6
EPDIR
This bit deï¬nes the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
5
DBLBUF
Logic 1 indicates that this endpoint has double buffering.
4
FFOISO
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a
bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0] Selects the buffer memory size according to Table 15.
9397 750 12337
Product data
Rev. 03 â 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
113 of 150
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