JDP2S01T Datasheet, PDF (138/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
20.2 DMA timing
20.2.1 HC single-cycle DMA timing
Table 153: Dynamic characteristics: HC single-cycle DMA timing
Symbol Parameter
Conditions
Read/write timing
t_RL
t_RLDV
t_RHDZ
t_WSU
t_WHD
t_AHRH
t_ALRL
T_DC
t_SHAH
t_RHAL
t_DS
RD pulse width
read process data set-up time
read process data hold time
write process data set-up time
write process data hold time
DACK1 HIGH to DREQ1 HIGH
DACK1 LOW to DREQ1 LOW
DREQ1 cycle
RD/WR HIGH to DACK1 HIGH
DREQ1 HIGH to DACK1 LOW
DREQ1 pulse spacing
[1] t_RHAL + t_DS +t_ALRL
ISP1362
Single-chip USB OTG controller
Min
Typ
Max
Unit
33
-
30
-
0
-
5
-
0
-
72
-
-
-
[1]
-
0
-
0
-
146
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
21
ns
-
ns
-
ns
-
ns
-
ns
DREQ1
DACK1
D [15:0]
(read)
T _DC
t _RHAL
t _ALRL
t _DS
t _SHAH
t _RLDV
data
valid
t _AHRH
t _RHDZ
D [15:0]
(write)
RD or WR
Fig 33. HC single-cycle DMA timing.
data
valid
t _WSU
t _WHD
004aaa107
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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