JDP2S01T Datasheet, PDF (14/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
8.9 GoodLink
Indication of a good USB connection is provided through the GoodLink technology
(open-drain, maximum current: 4 mA). During enumeration, LED indicators blink ON
momentarily corresponding to the enumeration traffic of the ISP1362 ports. The LED
also blinks ON whenever there is valid traffic to the USB ports. In the ‘suspend’ mode,
the LED is OFF.
This feature of GoodLink provides a user-friendly indication on the status of the USB
traffic between the host and the hub, as well as the connected devices. It is a useful
diagnostics tool to isolate faulty equipment and helps to reduce field support and
hotline costs.
8.10 Charge pump
The charge pump generates a 5 V supply from 3.3 V to drive V_BUS when the ISP1362
is an A-device in the OTG mode. For details, see Section 11.6.
9. Host and device bus interface
9397 750 12337
Product data
The interface between the external microprocessor and the ISP1362 Host Controller
(HC) and Device Controller (DC) is separately handled by the individual bus interface
circuitry. The host or device automux selects the path for the host access or the
device access. This selection is determined by the A1 address line. For any access
to HC or DC registers, the command phase and the data phase are needed, which is
determined by the A0 address line.
All the functionality of the ISP1362 can be accessed using a group of registers and
two buffer memory areas (one for the HC and the other the DC). Registers can be
accessed using the Programmed I/O (PIO) mode. The buffer memory can be
accessed using both the PIO and direct memory access (DMA) modes.
When CS is LOW (active), the address pin A1 has priority over DREQ and DACK.
Therefore, as long as the CS pin is held LOW, the ISP1362 bus interface does not
respond to any DACK signals. When CS is HIGH (inactive), the bus interface will
respond to DREQn and DACKn. The address pin A1 will be ignored when CS is
inactive.
An active DACKn signal when the DREQn is inactive will be ignored. If DREQ1,
DACK1, DREQ2 and DACK2 are active, the bus interface will be switched off to avoid
potential data corruption.
Table 3 provides the bus access priority for the ISP1362.
Table 3: Bus access priority table for the ISP1362
Priority CS
A1
DACK1 DACK2 DREQ1 DREQ2 HC and DC active
1
L
L
X
X
X
X
HC
2
L
H
X
X
X
X
DC
3
H
X
L
X
H
L
HC^[1]
4
H
X
X
L
L
H
DC^[1]
5
H
X
X
X
H
H
no driving
[1] Only for enabling of the bus and disabling of the bus. Depends only on the DACK signal.
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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