JDP2S01T Datasheet, PDF (66/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
14.4 OtgInterruptEnable register (R/W: 69H/E9H)
Code (Hex): 69 — read
Code (Hex): E9 — write
Table 28: OtgInterruptEnable register: bit allocation
Bit
15
14
13
12
Symbol
reserved
Reset
Access
Bit
Symbol
Reset
Access
-
-
7
OTG_
RESUME_
IE
0
R/W
-
-
6
OTG_
SUSPND_
IE
0
R/W
-
-
5
RMT_
CONN_IE
0
R/W
-
-
4
B_SESS_
VLD_IE
0
R/W
11
-
-
3
A_SESS_
VLD_IE
0
R/W
10
OTG_
TMR_IE
0
R/W
2
B_SESS_
END_IE
0
R/W
9
B_SE0_
SRP_IE
0
R/W
1
A_VBUS_
VLD_IE
0
R/W
8
A_SRP_
DET_IE
0
R/W
0
ID_REG_
IE
0
R/W
Table 29: OtgInterruptEnable register: bit description
Bit
Symbol Description
15 to 11 -
reserved
10
OTG_
Logic 1 enables interrupt when the OTG timer attains time-out.
TMR_IE
9
B_SE0_ Logic 1 enables interrupt upon detection of the B_SE0_SRP status
SRP_IE change.
8
A_SRP_ Logic 1 enables interrupt upon detection of the SRP event.
DET_IE
7
OTG_
Logic 1 enables interrupt upon detection of bus resume (J to K
RESUME_ only) event.
IE
6
OTG_
Logic 1 enables interrupt upon detection of the bus ‘suspend’
SUSPND_ status change.
IE
5
RMT_
Logic 1 enables interrupt upon detection of the RMT_CONN status
CONN_IE change.
4
B_SESS_ Logic 1 enables interrupt upon detection of B_SESS_VLD status
VLD_IE change.
3
A_SESS_ Logic 1 enables interrupt upon detection of A_SESS_VLD status
VLD_IE change.
2
B_SESS_ Logic 1 enables interrupt upon detection of B_SESS_END status
END_IE change.
1
A_VBUS_ Logic 1 enables interrupt upon detection of A_VBUS_VLD status
VLD_IE change.
0
ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status
change.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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