JDP2S01T Datasheet, PDF (9/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 2: Pin description…continued
Symbol^[1]
Pin
Ball
Type^[2]
LQFP64 TFBGA64
V_CC
14
J2
-
D12
15
J1
I/O
D13
16
K1
I/O
D14
17
K2
I/O
D15
18
J3
I/O
DGND
RD
19
K3
-
20
J4
I
CS
21
K4
I
WR
22
J5
I
TEST0
23
K5
I/O
DREQ1
24
J6
O
DREQ2
25
K6
O
Description
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
bit 12 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 13 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 14 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 15 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
digital ground
read strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a read to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
chip select input (active LOW); enables the HC/DC driver to access
the buffer memory and registers of the HC/DC
input
write strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a write to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
for test input and output; pulled HIGH by a 100 kΩ resistor
bidirectional, push-pull input, three-state output
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the HC; the active level (HIGH or LOW)
of the request is programmed by using the HcHardwareConfiguration
register (20H/A0H)
If the OneDMA bit of the HcHardwareConfiguration register is set to
logic 1, both the HC and DC DMA channel will be routed to DREQ1
and DACK1.
push-pull output
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the DC; the active level (HIGH or LOW)
of the request is programmed by using the DcHardwareConfiguration
register (BAH/BBH)
push-pull output
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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