JDP2S01T Datasheet, PDF (128/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 141: DcInterrupt register: bit description…continued
Bit
Symbol
Description
5
PSOF
Logic 1 indicates that an interrupt is issued every 1 ms because
of the Pseudo SOF; after three missed SOFs, the ‘suspend’
state is entered.
4
SOF
Logic 1 indicates that an SOF condition was detected.
3
EOT
Logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
2
SUSPND
Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state
was detected on the USB bus.
1
RESUME
Logic 1 indicates that a ‘resume’ state was detected.
0
RESET
Logic 1 indicates that a bus reset condition was detected.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
128 of 150