JDP2S01T Datasheet, PDF (54/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
13.3.4 Endpoint initialization
In response to the standard USB request Set Interface, the firmware must program all
the 16 ECRs of the DC in sequence (see Table 14), whether endpoints are enabled
or not. The hardware then automatically allocates buffer memory storage space.
If all endpoints have been successfully configured, the firmware must return an empty
packet to the control IN endpoint to acknowledge success to the host. If there are
errors in the endpoint configuration, the firmware must stall the control IN endpoint.
When reset by hardware or by the USB bus occurs, the DC disables all endpoints and
clears all ECRs, except the control endpoint which is fixed and always enabled.
An endpoint initialization can be done at any time. It is, however, valid only after
enumeration.
13.3.5 Endpoint I/O mode access
When an endpoint event occurs (a packet is transmitted or received), the associated
endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The
firmware then responds to the interrupt and selects the endpoint for processing.
The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR).
The ESR also contains information on the status of the endpoint buffer.
For an OUT (= receive) endpoint, the packet length and packet data can be read from
the DC by using the Read Buffer command. When the whole packet has been read,
the firmware sends a Clear Buffer command to enable the reception of new packets.
For an IN (= transmit) endpoint, the packet length and data to be sent can be written
to the DC by using the Write Buffer command. When the whole packet has been
written to the buffer, the firmware sends a Validate Buffer command to enable data
transmission to the host.
13.3.6 Special actions on control endpoints
Control endpoints require special firmware actions. The arrival of a Set-up packet
flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Set-up command to both the control
endpoints.
This ensures that the last Set-up packet stays in the buffer and that no packets can be
sent back to the host until the microprocessor has explicitly acknowledged that it has
received the Set-up packet.
13.4 DC direct memory access (DMA) transfer
DMA is a method to transfer data from one location to another in a computer system,
without intervention of the CPU. Many different implementations of DMA exist.
The DC supports the 8237 compatible mode.
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the
Intel 8237 DMA controller and has separate address spaces for memory and I/O.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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