JDP2S01T Datasheet, PDF (75/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 42: HcInterruptStatus register: bit description
Bit
Symbol Description
31 to 7
-
reserved
6
RHSC
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
5
FNO
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes from logic 0 to 1 or from logic 1
to 0.
4
UE
UnrecoverableError: This bit is set when the HC detects a
system error not related to the USB. The HC should not proceed
with any processing nor signaling before the system error has
been corrected. The HCD clears this bit after the HC has been
reset.
Philips Host Controller Interface (PHCI): Always set to logic 0.
3
RD
ResumeDetected: This bit is set when the HC detects that a
device on the USB is asserting resume signaling. It is the transition
from no resume signaling to resume signaling causing this bit to be
set. This bit is not set when the HCD sets the USBResume state.
2
SF
StartOfFrame: At the start of each frame, this bit is set by the HC
and an SOF is generated.
1
-
reserved
0
SO
SchedulingOverrun: This bit is set when the USB schedules for
current frame overruns. A scheduling overrun also causes the
SchedulingOverrunCount (SOC) of HcCommandStatus to be
incremented.
15.1.5 HcInterruptEnable register (R/W: 04H/84H)
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. When the following three
conditions occur:
• A bit is set in the HcInterruptStatus register
• The corresponding bit in the HcInterruptEnable register is set
• The MasterInterruptEnable (MIE) bit is set.
Then, a hardware interrupt is requested on the host bus.
Writing logic 1 to a bit in the HcInterruptEnable register sets the corresponding bit,
whereas writing logic 0 to a bit in this register leaves the corresponding bit
unchanged. On a read, the current value of this register is returned. Table 43 contains
the bit allocation of the register.
Code (Hex): 04 — read
Code (Hex): 84 — write
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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