JDP2S01T Datasheet, PDF (64/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 26:
Bit
Symbol
OtgInterrupt register: bit allocation
15
14
13
reserved
Reset
Access
Bit
Symbol
Reset
Access
-
-
7
OTG_
RESUME
0
R/W
-
-
6
OTG_
SUSPND
0
R/W
-
-
5
RMT_
CONN_C
0
R/W
12
-
-
4
B_SESS_
VLD_C
0
R/W
11
-
-
3
A_SESS_
VLD_C
0
R/W
10
OTG_TMR
_TIMEOUT
0
R/W
2
B_SESS_
END_C
0
R/W
9
B_SE0_
SRP
0
R/W
1
A_VBUS_
VLD_C
0
R/W
8
A_SRP_
DET
0
R/W
0
ID_REG_C
0
R/W
Table 27: OtgInterrupt register: bit description
Bit
Symbol
Description
15 to 11 -
reserved
10
OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing
TIMEOUT logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — OTG Timer time-out
9
B_SE0_ This bit is set whenever the device detects more than 2 ms of SE0.
SRP
Writing logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — bus has been in SE0 for more than 2 ms
8
A_SRP_ This bit is used to detect the session request event (SRP) from the
DET
remote device. The SRP event can be either V_BUS pulsing or data
line pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register
determines which SRP is selected. Writing logic 1 clears this bit.
Writing logic 0 has no effect.
0 — no event
1 — SRP is detected
7
OTG_
This bit is used to detect a J to K state change when the device is
RESUME in the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0
has no effect.
0 — no event
1 — a resume signal (J → K) is detected when the bus is in the
‘suspend’ state
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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