JDP2S01T Datasheet, PDF (78/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 46: HcInterruptDisable register: bit description…continued
Bit
Symbol Description
2
SF
0 — ignore
1 — disable interrupt generation because of Start of Frame
1
-
reserved
0
SO
0 — ignore
1 — disable interrupt generation because of Scheduling Overrun
15.2 HC Frame Counter registers
15.2.1 HcFmInterval register (R/W: 0DH/8DH)
The HcFmInterval register (bit allocation: Table 47) contains a 14-bit value that
indicates the bit time interval in a frame between two consecutive SOFs. In addition, it
contains a 15-bit value indicating the full-speed maximum packet size that the HC
may transmit or receive without causing a scheduling overrun. The HCD may carry
out minor adjustments on FrameInterval by writing a new value over the present one
at each SOF. This provides the programmability necessary for the HC to synchronize
with an external clocking resource and to adjust any unknown local clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Table 47: HcFmInterval register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FIT
FSMPS[14:8]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
FSMPS[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FI[13:8]
Reset
-
-
1
0
1
1
1
0
Access
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FI[7:0]
Reset
1
1
0
1
1
1
1
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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