JDP2S01T Datasheet, PDF (74/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 40: HcCommandStatus register: bit description
Bit
Symbol Description
31 to 18 -
reserved
17 to 16
SOC[1:0]
SchedulingOverrunCount: This field is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It needs to be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by the HCD to monitor any
persistent scheduling problems.
15 to 1
-
reserved
0
HCR
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of
the HC, it moves to the USBSuspend state in which most of the
operational registers are reset except those stated otherwise. This
bit is cleared by the HC on completing the reset operation. The
reset operation must be completed within 10 ms. This bit, when
set, should not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream ports.
15.1.4 HcInterruptStatus register (R/W: 03H/83H)
This register (bit allocation: Table 41) provides the status of the events that cause
hardware interrupts. When an event occurs, the HC sets the corresponding bit in this
register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled
in the HcInterruptEnable register (see Section 15.1.5) and the MasterInterruptEnable
(MIE) bit is set. The HCD may clear specific bits in this register by writing logic 1 to
the bit positions to be cleared. The HC, however, does not clear the bit. The HCD may
not set any of these bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Table 41: HcInteruptStatus register: bit allocation
Bit
31
30
29
Symbol
Reset
-
-
-
Access
-
-
-
Bit
23
22
21
Symbol
Reset
-
-
-
Access
-
-
-
Bit
15
14
13
Symbol
Reset
-
-
-
Access
-
-
-
Bit
7
6
5
Symbol
reserved
RHSC
FNO
Reset
-
0
0
Access
-
R/W
R/W
28
27
reserved
-
-
-
-
20
19
reserved
-
-
-
-
12
11
reserved
-
-
-
-
4
3
UE
RD
0
0
R/W
R/W
26
25
24
-
-
-
-
-
-
18
17
16
-
-
-
-
-
-
10
9
8
-
-
-
-
-
-
2
1
0
SF
reserved
SO
0
-
0
R/W
-
R/W
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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