JDP2S01T Datasheet, PDF (139/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
20.2.2 HC burst mode DMA timing
Table 154: Dynamic characteristics: HC burst mode DMA timing
Symbol Parameter
Conditions
Read/write timing (for 4-cycle and 8-cycle burst mode)
t_RL
t_RHRL
T_RC
t_SLRL
t_SHAH
t_RHAL
T_DC
t_DS(read)
WR/RD LOW pulse width
WR/RD HIGH to next WR/RD LOW
WR/RD cycle
RD/WR LOW to DREQ1 LOW
RD/WR HIGH to DACK1 HIGH
DREQ1 HIGH to DACK1 LOW
DREQ1 cycle
DREQ1 pulse spacing (read)
4-cycle burst mode
8-cycle burst mode
t_DS(write) DREQ1 pulse spacing (write)
4-cycle burst mode
8-cycle burst mode
[1] t_SLAL + (4 or 8)t_RC + t_DS
ISP1362
Single-chip USB OTG controller
Min
Typ
Max
Unit
42
-
60
-
102
-
22
-
0
-
0
-
[1]
-
105
-
150
-
72
-
167
-
-
ns
-
ns
-
ns
64
ns
-
ns
ns
-
ns
-
ns
-
ns
-
ns
-
ns
DREQ1
DACK1
t _RHSH
t _RHAL
t _RHRL
RD or WR
T _RC
t _RLRH
Fig 34. HC burst mode DMA timing.
t _SLRL
t _DS
t _SHAH
004aaa108
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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