JDP2S01T Datasheet, PDF (123/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 127: DcEndpointStatusImage register: bit description…continued
Bit
Symbol
Description
3
OVERWRITE This bit is set by hardware. Logic 1 indicates that a new Set-up
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the set-up data has finished.
Firmware must check this bit before sending an Acknowledge
Set-up command or stalling the endpoint. Upon reading logic 1,
the firmware must stop ongoing set-up actions and wait for a
new Set-up packet.
2
SETUPT
Logic 1 indicates that the buffer contains a Set-up packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer; 1 = secondary buffer).
0
-
reserved
16.2.7 Acknowledge Set-up (F4H)
This command acknowledges to the host that a Set-up packet was received. The
arrival of a Set-up packet disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Set-up command, see Section 13.3.6.
Code (Hex): F4 — acknowledge set-up
Transaction — none (code only)
16.3 General commands
16.3.1 Read Endpoint Error Code (R: A0H–AFH)
This command returns the status of the last transaction of the selected endpoint, as
stored in the DcErrorCode register. Each new transaction overwrites the previous
status information. The bit allocation of the DcErrorCode register is shown in
Table 128.
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte (code or data)
Table 128: DcErrorCode register: bit allocation
Bit
7
6
5
4
Symbol
UNREAD DATA01 reserved
Reset
0
0
-
0
Access
R
R
-
R
3
2
ERROR[3:0]
0
0
R
R
1
0
RTOK
0
0
R
R
Table 129: DcErrorCode register: bit description
Bit
Symbol
Description
7
UNREAD
Logic 1 indicates that a new event occurred before the previous
status was read.
6
DATA01
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID; 1 = DATA1 PID).
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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