JDP2S01T Datasheet, PDF (59/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
The DC in the ISP1362 will remain in the suspend state for at least 5 ms, before
responding to external wake-up events, such as global resume, bus traffic, CS active
or LOW pulse on the D_SUSPEND/D_WAKEUP pin.
Figure 27 shows a typical timing diagram for the DC suspend and resume operations.
USB BUS
INT2
GOSUSP (bit)
A
> 5 ms
idle state
> 3 ms
suspend
interrupt
B
D
10 ms
K-state
resume
interrupt
D_SUSPEND/D_WAKEUP
1.8 ms to
2.2 ms
0.5 ms to
3.5 ms
CS
C
004aaa483
Fig 27. Suspend and resume timing.
In Figure 27:
A — indicates the point at which the USB bus goes to the idle state.
B — after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode
register.
C — indicates resume condition, which can be a resume signal from the host, a LOW
pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.
D — indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for
10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW.
13.5.2 Resume conditions
Wake-up from the suspend state is initiated either by the USB host or by the
application:
• USB host: drives a K-state on the USB bus (global resume)
• Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP
or a LOW pulse on pin CS (if enabled using bit WKUPCS of the
DcHardwareConfiguration register).
The steps of a wake-up sequence are as follows:
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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