JDP2S01T Datasheet, PDF (69/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
15. HC registers
The HC contains a set of on-chip control registers. These registers can be read or
written by the HC Driver (HCD). The Control and Status register set, the Frame
Counter register set and the Root Hub register set are grouped under the category of
HC operational registers (32 bits). These operational registers are made compatible
to Open Host Controller Interface (OpenHCI) operational registers. This enables the
OpenHCI HCD to be ported easily to the ISP1362.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD that does not use a reserved field must not assume that the
reserved field contains logic 0. Furthermore, the HCD must always preserve the
values of the reserved field. When a R/W register is modified, the HCD must first read
the register, modify the desired bits and then write the register with the reserved bits
still containing the read value. Alternatively, the HCD can maintain an in-memory
copy of previously written values that can be modified and then written to the
HC register. When there is a write to set or clear the register, bits written to reserved
fields must be logic 0.
As shown in Table 34, the offset locations (the commands for reading registers) of
these operational registers (32-bit registers) are similar to those defined in the OHCI
specification. The addresses, however, are equal to offset divided by 4.
Table 34: HC Control registers summary
Command (Hex)
Register
Read
Write
00
N/A
HcRevision
01
81
HcControl
02
82
HcCommandStatus
03
83
HcInterruptStatus
04
84
HcInterruptEnable
05
85
HcInterruptDisable
0D
8D
HcFmInterval
0E
8E
HcFmRemaining
0F
8F
HcFmNumber
11
91
HcLSThreshold
12
92
HcRhDescriptorA
13
93
HcRhDescriptorB
14
94
HcRhStatus
15
95
HcRhPortStatus[1]
16
96
HcRhPortStatus[2]
20
A0
HcHardwareConfiguration
21
A1
HcDMAConfiguration
22
A2
HcTransferCounter
24
A4
HcµPInterrupt
25
A5
HcµPInterruptEnable
Width Reference
Functionality
32
Section 15.1.1 on page 71 HC Control and Status
32
Section 15.1.2 on page 71 ^registers
32
Section 15.1.3 on page 73
32
Section 15.1.4 on page 74
32
Section 15.1.5 on page 75
32
Section 15.1.6 on page 76
32
Section 15.2.1 on page 78 HC Frame Counter
32
Section 15.2.2 on page 79 ^registers
32
Section 15.2.3 on page 80
32
Section 15.2.4 on page 81
32
Section 15.3.1 on page 82 HC Root Hub registers
32
Section 15.3.2 on page 84
32
Section 15.3.3 on page 85
32
Section 15.3.4 on page 87
32
Section 15.3.4 on page 87
16
Section 15.4.1 on page 92 HC DMA and Interrupt
16
Section 15.4.2 on page 94 ^{Control registers}
16
Section 15.4.3 on page 95
16
Section 15.4.4 on page 95
16
Section 15.4.5 on page 97
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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