JDP2S01T Datasheet, PDF (92/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
15.4 HC DMA and interrupt control registers
15.4.1 HcHardwareConfiguration register (R/W: 20H/A0H)
The bit allocation of the HcHardwareConfiguration register is given in Table 63.
Code (Hex): 20 — read
Code (Hex): A0 — write
Table 63: HcHardwareConfiguration register: bit allocation
Bit
15
14
13
12
11
Symbol
Disable
Suspend_
Wakeup
Global
Power
Down
Connect
PullDown
_DS2
Connect
PullDown
_DS1
Suspend
ClkNotStop
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
Symbol
OneDMA DACKInput
Polarity
DREQ
Output
Polarity
DataBusWidth[1:0]
Reset
0
0
1
0
1
Access
R/W
R/W
R/W
R/W
R/W
10
AnalogOC
Enable
0
R/W
2
Interrupt
Output
Polarity
0
R/W
9
8
OneINT DACKMode
0
R/W
1
Interrupt
PinTrigger
0
R/W
0
InterruptPin
Enable
0
0
R/W
R/W
Table 64: HcHardwareConfiguration register: bit description
Bit
Symbol
Description
15
DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the
D_SUSPEND/D_WAKEUP and
H_SUSPEND/H_WAKEUP pins. Therefore, these pins
will always remain HIGH and pulling them LOW does
not wake up the HC and the DC.
14
GlobalPowerDown
Set this bit to logic 1 to reduce power consumption of
the OTG ATX in the suspend mode.
13
ConnectPullDown_DS2 0 — disconnect built-in pull-down resistors on H_DM2
and H_DP2
1 — connect built-in pull-down resistors on H_DM2
and H_DP2 for the downstream port 2
Remark: Port 2 is always used as a host port.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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