JDP2S01T Datasheet, PDF (94/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
15.4.2 HcDMAConfiguration register (R/W: 21H/A1H)
Table 65 contains the bit allocation of the HcDMAConfiguration register.
Code (Hex): 21 — read
Code (Hex): A1 — write
Table 65: HcDMAConfiguration register: bit allocation
Bit
15
14
13
12
11
10
9
Symbol
reserved
Reset
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
Symbol
DMACounter
Enable
BurstLen[1:0]
DMA
Enable
Buffer_Type_Select[2:0]
Reset
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
-
-
0
DMARead
WriteSelect
0
R/W
Table 66: HcDMAConfiguration register: bit description
Bit
Symbol
Description
15 to 8 -
reserved
7
DMACounterEnable 0 — reserved
1 — DMA counter is enabled. Once the counter is
enabled, the HCD must initialize the HcTransferCounter
register to a non-zero value for DREQ to be raised after
the DMAEnable bit is set to HIGH.
6 to 5
BurstLen[1:0]
00 — single-cycle burst DMA
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
4
3 to 1
0
DMAEnable
Buffer_Type_Select
[2:0]
DMAReadWriteSelect
11 — reserved
I/O bus with 32-bit data path width supports only single
and four cycle DMA burst.
0 — DMA is disabled
1 — DMA is enabled
This bit needs to be reset when the DMA transfer is
completed.
Bit 3 Bit 2 Bit 1 Buffer Type
0
0
0
ISTL0 (default)
0
0
1
ISTL1
0
1
0
INTL
0
1
1
ATL
1
X
X
Direct Addressing
0 — read from the buffer memory of the HC
1 — write to the buffer memory of the HC
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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