JDP2S01T Datasheet, PDF(120/150 Page) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

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JDP2S01T Datasheet, PDF (120/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

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Philips Semiconductors

ISP1362

Single-chip USB OTG controller

Code (Hex): 01 to 0F â write (control IN, endpoint 1 to 14)

Code (Hex): 10, 12 to 1F â read (control OUT, endpoint 1 to 14)

Transaction â write or read maximum N + 2 bytes (isochronous endpoint: N â¤ 1023,

bulk/interrupt endpoint: N â¤ 32) (code or data)

The data in the endpoint buffer memory must be organized as shown in Table 122. An

example of endpoint buffer memory access is given in Table 123.

Table 122: Endpoint buffer memory organization

Word #

Description

0 (lower byte)

packet length (lower byte)

0 (upper byte)

packet length (upper byte)

1 (lower byte)

data byte 1

1 (upper byte)

data byte 2

â¦

M = (N + 1)/2

data byte N

Table 123: Example of endpoint buffer memory access

Phase

Bus lines Word # Description

HIGH command D[7:0]

command code (00H to 1FH)

D[15:8]

ignored

LOW data

D[15:0]

packet length

LOW data

D[15:0]

data word 1 (data byte 2, data byte 1)

LOW data

D[15:0]

data word 2 (data byte 4, data byte 3)

â¦

Remark: There is no protection against writing or reading past a bufferâs boundary,

against writing into an OUT buffer or reading from an IN buffer. Any of these actions

could cause an incorrect operation. Data residing in an OUT buffer is only meaningful

after a successful transaction. Exception: during DMA access of a double-buffered

endpoint, the buffer pointer automatically points to the secondary buffer after

reaching the end of the primary buffer.

16.2.2 Read Endpoint Status (R: 50Hâ5FH)

This command is used to read the status of an endpoint buffer memory. The

command accesses the DcEndpointStatus register, the bit allocation of which is

shown in Table 124. Reading the DcEndpointStatus register will clear the interrupt bit

set for the corresponding endpoint in the DcInterrupt register (see Table 140).

All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by

the Stall or Unstall commands and by the reception of a SET-UP token (see

Section 16.2.3).

Code (Hex): 50 to 5F â read (control OUT, control IN, endpoint 1 to 14)

Transaction â read 1 byte (code only)

9397 750 12337

Product data

Rev. 03 â 06 January 2004

120 of 150

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