JDP2S01T Datasheet, PDF (100/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Table 76: HcBufferStatus register: bit description…continued
Bit
Symbol
Description
7
-
reserved
6
ISTL1_ActiveStatus 0 — The ISTL1 buffer is not accessed by the slave host.
1 — The ISTL1 buffer is accessed by the slave host.
5
ISTL0_ActiveStatus 0 — The ISTL0 buffer is not accessed by the slave host.
1 — The ISTL0 buffer is accessed by the slave host.
4
Reset_HW
PingPong
Reg
0 to 1 — resets internal hardware ping pong register to 0
when ATL_Active is 0. The hardware ping pong register
can be read from bit 10 of this register.
1 to 0 — has no effect.
3
ATL_Active
0 — The HC does not process the ATL buffer.
1 — The HC processes the ATL buffer.
2
INTL_Active
0 — The HC does not process the INTL buffer.
1 — The HC processes the INTL buffer.
1
ISTL1BufferFull
0 — The HC does not process the ISTL1 buffer.
1 — The HC processes the ISTL1 buffer.
0
ISTL0BufferFull
0 — The HC does not process the ISTL0 buffer.
1 — The HC processes the ISTL0 buffer.
15.6.2 HcDirectAddressLength register (R/W: 32H/B2H)
The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL
or ATL buffers. This register specifies the starting address of the buffer and byte count
of the data to be addressed. Therefore, it allows the programmer to randomly access
the buffer. The bit allocation of the register is given in Table 77.
Code (Hex): 32 — read
Code (Hex): B2 — write
Table 77: HcDirectAddressLength register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
DataByteCount[15:8]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
DataByteCount[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BufferStartAddress[14:8]
Reset
0
0
0
0
0
0
0
0
Access
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 12337
Product data
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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