JDP2S01T Datasheet, PDF (29/150 Pages) Toshiba Semiconductor – UHF~VHF Band RF Attenuator Applications

Philips Semiconductors
ISP1362
Single-chip USB OTG controller
9397 750 12337
Product data
The interrupt level 2 (OPR group) contains six possible interrupt events (recorded in
the HcInterruptStatus register). When any of these events occurs, the corresponding
bit would be set to logic 1, and if the corresponding bit in the HcInterruptEnable
register is also logic 1, the 6-input OR gate would output logic 1. This output is
combined with the value of MIE (bit 31 of HcInterruptEnable) using the AND
operation and logic 1 output at this AND gate will cause the OPR bit in the
HcµPInterrupt register to be set to logic 1.
The interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in
the OtgInterrupt register). When any of these events occurs, the corresponding bit
would be set to logic 1, and if the corresponding bit in the OtgInterruptEnable register
is also logic 1, the 11-input OR gate would output logic 1 and cause the OTG_IRQ bit
in the HcµPInterrupt register to be set to logic 1.
The level 1 interrupts contains 10 possible interrupt events. The HcµPInterrupt and
HcµPInterruptEnable registers work in the same way as the HcInterruptStatus and
HcInterruptEnable registers. The output from the 10-input OR gate is connected to a
latch, which is controlled by InterruptPinEnable (the bit 0 of HcHardwareConfiguration
register).
When the software wishes to temporarily disable the interrupt output of the
ISP1362 HC and OTGC, follow this procedure:
1. Set the InterruptPinEnable bit in HcHardwareConfiguration register to logic 1.
2. Clear all bits in the HcµPInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1.
Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register
controls the latch of the interrupt output. When this bit is set to logic 0, the interrupt
output will remain unchanged, regardless of any operation on the interrupt control
registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal
without clearing the HcµPInterrupt register, follow this procedure:
1. Make sure that the InterruptPinEnable bit is set to logic 1.
2. Clear all bits in the HcµPInterruptEnable register.
3. Set the InterruptPinEnable bit to logic 0.
To re-enable the interrupt generation:
1. Set all bits in the HcµPInterruptEnable register according to the HCD
requirements.
2. Set the InterruptPinEnable bit to logic 1.
9.7.2 Interrupt in the DC
The registers that control the interrupt generation in the ISP1362 DC are:
• DcMode (bit 3)
• DcHardwareConfiguration (bits 0 and 1)
Rev. 03 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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