TLK3131_15 Datasheet, PDF (95/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
A.1 Recovered Byte Clock Jitter Cleaner Mode:
If it is desired to dedicate the Jitter Cleaner PLL to clean the RX SERDES recovered byte clock, then the
following procedure must be followed:
1. Program REF_SEL[1:0] to 2’b10.
2. Program RXB_SEL[1:0] to 2’b00.
3. Program RX_SEL to 2’b10 -or- 2’b11.
4. Program TX_SEL as desired.
5. Program 16.10:9 as desired on a per channel basis.
6. Consult the rows in the appropriate Appendix A table to find the appropriate REFCLK and SERDES
mode settings. Note that only rows indicating that the Jitter Cleaner PLL is OFF may be used.
Provision the SERDES settings appropriately.
7. Divide the selected SERDES serial rate by 8 if in EBI/REBI modes, or 10 otherwise, and use that
frequency as the input to Figure A-9 Recovered Byte Clock Jitter Cleaner Mode, to determine the
appropriate Jitter Cleaner PLL settings. Note that only a 1:1 frequency ratio is supported between the
SERDES output byte clock and the parallel interface output recovered byte clock. Depending upon the
selection of TX_SEL, it may also be necessary to provision RXTX_DIV with the same value as
RXB_DIV.
Copyright © 2008–2009, Texas Instruments Incorporated
APPENDIX A – Frequency Ranges Supported
95
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