TLK3131_15 Datasheet, PDF (7/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
2-47 SERDES_PLL_STATUS ........................................................................................................ 42
2-48 JC_CLOCK_MUX_CONTROL.................................................................................................. 43
2-49 JC_VTP_CLK_DIV_CONTROL ................................................................................................ 43
2-50 JC_DELAY_STOPWATCH_CLK_DIV_CONTROL .......................................................................... 44
2-51 JC_DELAY_STOPWATCH_COUNTER....................................................................................... 44
2-52 JC_REFCLK_FB_DIV_CONTROL............................................................................................. 44
2-53 JC_RXB_OUTPUT_CLK_DIV_CONTROL ................................................................................... 44
2-54 JC_CHARGE_PUMP_CONTROL ............................................................................................. 45
2-55 Charge Pump Control Setting (CP_CTRL) ................................................................................... 45
2-56 JC_PLL_CONTROL.............................................................................................................. 45
2-57 JC_TEST_CONTROL_1 ........................................................................................................ 46
2-58 JC_TEST_CONTROL_2 ........................................................................................................ 46
2-59 JC_TI_TEST_CONTROL_1..................................................................................................... 46
2-60 JC_TI_TEST_CONTROL_2..................................................................................................... 46
2-61 JC_TRIM_STATUS .............................................................................................................. 46
2-62 DIE_ID_7 .......................................................................................................................... 46
2-63 DIE_ID_6 .......................................................................................................................... 47
2-64 DIE_ID_5 .......................................................................................................................... 47
2-65 DIE_ID_4 .......................................................................................................................... 47
2-66 DIE_ID_3 .......................................................................................................................... 47
2-67 DIE_ID_2 .......................................................................................................................... 47
2-68 DIE_ID_1 .......................................................................................................................... 47
2-69 DIE_ID_0 .......................................................................................................................... 47
2-70 EFUSE_STATUS................................................................................................................. 47
2-71 EFUSE_CONTROL .............................................................................................................. 48
2-72 HSTL_INPUT_TERMINATION_CONTROL................................................................................... 48
2-73 HSTL_OUTPUT_SLEWRATE_CONTROL ................................................................................... 48
2-74 HSTL_INPUT_VTP_CONTROL ................................................................................................ 48
2-75 HSTL_OUTPUT_VTP_CONTROL ............................................................................................. 49
2-76 HSTL_GLOBAL_CONTROL .................................................................................................... 49
2-77 TX0_DLL_CONTROL............................................................................................................ 50
2-78 TX1_DLL_CONTROL............................................................................................................ 50
2-79 RX0_DLL_CONTROL ........................................................................................................... 50
2-80 RX1_DLL_CONTROL ........................................................................................................... 50
2-81 DLL Offset Control ............................................................................................................... 51
2-82 TX0_DLL_STATUS .............................................................................................................. 51
2-83 TX1_DLL_STATUS .............................................................................................................. 51
2-84 RX0_DLL_STATUS .............................................................................................................. 51
2-85 RX1_DLL_STATUS .............................................................................................................. 51
2-86 CH0_TESTFAIL_ERR_COUNTER ............................................................................................ 51
2-87 CH1_TESTFAIL_ERR_COUNTER ............................................................................................ 51
2-88 STCI_CONTROL_STATUS..................................................................................................... 52
2-89 TESTCLK_CONTROL ........................................................................................................... 52
2-90 BIDI_CMOS_CONTROL ........................................................................................................ 52
2-91 DEBUG_CONTROL.............................................................................................................. 52
2-92 DUTY_CYCLE_CONTROL ..................................................................................................... 52
3-1 Global Signals .................................................................................................................... 60
3-2 JTAG Signals ..................................................................................................................... 61
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