TLK3131_15 Datasheet, PDF (36/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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BIT(s)
17.0
Table 2-19. PHY_CH_CONTROL_2 (continued)
ADDRESS: 0x11
DEFAULT: 0x3590
NAME
DESCRIPTION
When channel is in SDR mode
1 = Rising edge align mode. Incoming parallel data is aligned to rising edge of
parallel input clock. Internally data is latched at the falling edge of the clock.
0 = Falling edge align mode. Incoming data is aligned to falling edge of parallel
input clock. Internally data is latched at the rising edge of the clock
RX Edge Mode
When channel is in DDR mode
1 = Source aligned timing on receive parallel interface. Data changes at clock
edge.
0 = Source centered timing on receive parallel interface.
When channel is in SDR mode
1 = Rising edge align mode. Outgoing parallel data is aligned to the rising edge of
the parallel output clock
0 = Falling edge align mode. Outgoing parallel data is aligned to the falling edge of
the parallel output clock
ACCESS
RW
Table 2-20. PHY_RX_CTC_FIFO_STATUS
BIT(s)
18.15
18.14
18.13
ADDRESS: 0x12
DEFAULT: 0x0000
NAME
DESCRIPTION
RX_CTC_Reset
When high indicates overflow or underflow has occurred in CTC FIFO and FIFO
has been reset.
RX_CTC_Insert
When high indicates RX CTC has inserted at least one ordered set.
RX_CTC_Delete
When high indicates RX CTC has deleted at least one ordered set.
ACCESS
RO/LH
Table 2-21. PHY_TX_CTC_FIFO_STATUS
BIT(s)
19.15
ADDRESS: 0x13
DEFAULT: 0x0000
NAME
DESCRIPTION
TX_FIFO_Reset_1Gx
When high indicates collision has occurred in TX FIFO and the FIFO is reset in 1gx
mode. Valid in Non-NBID, Non-TBID modes.
ACCESS
RO/LH
Table 2-22. PHY_TX_WIDE_FIFO _STATUS
BIT(s)
20.15
20.14
ADDRESS: 0x14
NAME
TX_WIDE_FIFO_Overflow
TX_WIDE_FIFO_Underflow
DEFAULT: 0x0000
DESCRIPTION
When high indicates Overflow condition has occurred in TX WIDE FIFO. Valid
only when device is in NBID/TBID modes.
When high indicates Underflow condition has occurred in TX WIDE FIFO. Valid
only when device is in NBID/TBID modes.
ACCESS
RO/LH
Table 2-23. PHY_TEST_PATTERN_SYNC_STATUS
BIT(s)
21.1
21.0
ADDRESS: 0x15
DEFAULT: 0x0000
NAME
DESCRIPTION
Test Pattern Sync
When high indicates alignment has been determined and a correct pattern has been
received for fixed test patterns.
CRPAT Sync
When high indicates alignment has been determined and a correct pattern has been
received for continuous test patterns.
ACCESS
RO
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