TLK3131_15 Datasheet, PDF (29/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

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TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
TDP
50 W transmission line
RDP
VDDT 0.8*VDDT
DIR
AC
50
COUP COUP
50
GND
TRANSMITTER
TDN
50 W transmission line
MEDIA
RDN
RECEIVER
Figure 2-19. Example High Speed I/O AC Coupled Mode
Current Mode Logic (CML) drivers often require external components. The disadvantage of the external
component is a limited edge rate due to package and line parasitic. The CML driver on TLK3131 has
on-chip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased
speed requirements. The transmitter output driver is highly configurable allowing output amplitude and
de-emphasis to be tuned to a channel's individual requirements. Software programmability allows for
flexible output amplitude control. AC Coupled and Direct Coupled modes are supported. When AC
coupling is selected, the receiver input is internally biased 0.8×VDDT which is the optimum voltage for
input sensitivity. As the input and output references are derived from VDDT, the tolerance of this supply
will dominate the accuracy of the internal reference.
When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal
is attenuated due to the skin effect of the media. This causes a “smearing” of the data eye when viewed
on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In
order to provide equalization for the high frequency loss, 1-tap finite impulse response (FIR) transmit
de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by
allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. A total of
15 de-emphasis settings and 8 output amplitude settings can be independently selected.
V
CMT
V_OD(p)
V_OD(d)
V_OD(pd) V_OD(pp)
V_OD(d)
bit
bit
time
time
V_OD(p)
Figure 2-20. Output Differential Voltage With 1-Tap FIR De-emphasis
The level of de-emphasis is programmable via MDIO Register bits. Users can control the strength of the
de-emphasis to optimize for a specific system requirement.
2.7.15 High Speed Receiver
The high speed receiver conforms to the physical layer requirements of IEEE 802.3ae Clause 47(XAUI),
Copyright © 2008–2009, Texas Instruments Incorporated
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