TLK3131_15 Datasheet, PDF (39/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 2-34. SERDES_RATE_CONFIG_TX_RX
BIT(s)
36865.15:14
36865.13:12
36865.7:6
36865.5:4
ADDRESS: 0x9001
DEFAULT: 0x0000
NAME
DESCRIPTION
RATE_0_TX
TX Ch 0 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
Reserved
Reserved
RATE_0_RX
RX Ch 0 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
Reserved
Reserved
ACCESS
RW
RW
RW
RW
Table 2-35. SERDES_RX0_CONFIG⁽¹⁾
ADDRESS: 0x9002
DEFAULT: 0x0001
BIT(s)
NAME
DESCRIPTION
36866.15:12
EQUALIZER
Adaptive equalization control
0000 = Adaptive equalization disabled. Equalizer provides flat response at maximum
gain.
0001 = Full adaptive equalization
0010 to 1111 = Reserved
36866.11:9
CDR
Clock data recovery algorithm selection
36866.8
INVPAIR
1 = Inverts polarity of RXP and RXN
36866.7:6
LOS
00 = Loss of signal detection disabled
01 = Reserved
10 = Loss of signal detection enabled with threshold in the range of 85-175 mVdfpp.
11 = Reserved.
36866.5:4
ALIGN
Receiver symbol alignment selection
00 = Alignment disabled.
01 = Comma alignment enabled
10 = Symbol alignment will be performed by one bit position when this mode is
selected (i.e ALIGN changes from 00 to 10)
11= Reserved
36866.3:2
TERM
Receive Termination selection
00 = Common point connected to VDDT (For DC Coupled Systems)
01 = Common point set to 0.8 VDDT (For AC Coupled Systems)
10 = Reserved
11 = Reserved
36866.1
ENTEST
1= Enables test modes specified in TESTCFG (Register 0x9012)
36866.0
ENRX
1 = Enables receiver
0 = Disables receiver
(1) These are SERDES receiver control bits for channel 0.
Table 2-36. SERDES_RX1_CONFIG⁽¹⁾
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
ADDRESS: 0x9004
BIT(s)
NAME
36868.15:12 Reserved
Reserved
(1) These are SERDES receiver control bits for channel 1.
DESCRIPTION
DEFAULT: 0x0001
ACCESS
RW
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Detailed Description
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