TLK3131_15 Datasheet, PDF (33/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
2.8 PROGRAMMERS REFERENCE
Following registers can be addressed directly only through Clause 22. These bits are per channel basis.
Channel identification is based on PHY (Port) address field.
Channel 0 can be accessed by setting LSB of PHY address to 0.
Channel 1 can be accessed by setting LSB of PHY address to 1 (access is only required during device
initialization per the software bring up procedure).
Table 2-13. PHY_CONTROL_1
BIT(s)
0.15
0.14
0.13
0.12
0.11
0.10
0.9
0.8
0.7
0.6
ADDRESS: 0x00
DEFAULT: 0x0140
NAME
DESCRIPTION
Reset
1 = PHY reset (including all registers and Tx/Rx datapath)
0 = Normal operation (Default 1’b0)
This is a global bit (not per channel). Asserting this bit is equivalent to asserting the
device primary input RST_N.
Loopback
Logically OR’ed with PLOOP
1 = Enable loop back mode. In this mode, serial output of the channel is looped
back onto serial input.
0 = Disable loop back mode (Default 1’b0)
Speed Selection(LSB)
This is the least significant bit of the speed selection bits (MSB is 0.6). {0.6,0.13} =
2’b10 1000Base-X Rate This bit always reads 0.
Auto-Negotiation Enable Always reads 0. (Auto-Negotiation not supported)
Power Down
Setting this bit high powers down the channel, with exception that MDIO interface
stays active. Serdes PLL’s can be shut down by de-asserting bits 36864.12 and
36864.4. Jitter cleaner PLL can be shut down by de-asserting 37127.15
1 = Power Down mode is enabled.
0 = Normal operation (Default 1’b0)
Isolate
Setting this bit high isolates the channel from the parallel interface. Inputs are
ignored; Outputs are set to high impedance. 1 = Isolate is enabled 0 = Normal
operation (Default 1’b0)
Restart Auto-Negotiation Always reads 0. (Auto-Negotiation not supported)
Duplex Mode
Always reads 1. (Only Full duplex supported)
Collision Test
Not Applicable. Read will return a 0.
Speed Selection (MSB)
This is the most significant bit of the speed selection bits (LSB is 0.13).
{0.6,0.13} = 2’b10 1000Base-X Rate. This bit always reads 1
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
ACCESS
RW
SC ⁽¹⁾
RW
RO
RO
RW
RW
RO
RO
RO
RO
Table 2-14. PHY_STATUS_1
BIT(s)
1.15
1.14
1.13
1.12
1.11
1.10
1.9
1.8
1.6
1.5
1.4
1.3
ADDRESS: 0x01
DEFAULT: 0x0101
NAME
DESCRIPTION
1000Base-T4
Always reads 0
100Base-X FD
Always reads 0
100Base-X HD
Always reads 0
10Mb/s FD
Always reads 0
10Mb/s HD
Always reads 0
100Base-T2 FD
Always reads 0
100Base-T2 HD
Always reads 0
Extended Status
Read will return 1 indicating extended status information is held in register 0x0F.
MF Prea Supp
Read will return 0 indicating MDIO doesn’t accept command without preceding preamble
(minimum 32 1’s). Writes will be ignored
AN Complete
Always reads 0 (AN not supported)
Remote Fault
Always reads 0
AN Ability
Read will return 0, indicating that Auto negotiation is not supported
ACCESS
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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