TLK3131_15 Datasheet, PDF (18/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
2.7.2 RTBI Mode (Reduced Ten Bit Interface)
Table 2-4. RTBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
Channel 0
TRANSMIT DATA 5 BITS
(INPUT)
TXC_[4:0]
RECEIVE DATA 5 BITS
(OUTPUT)
RXD_[4:0]
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
TXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXD_[4:0]
Data0[4:0]
Data0[9:5]
DDR Source Centered Timing
(Nibble Order = 0)
TXCLK_[0]
TXD_[4:0]
Data0[9:5]
Data0[4:0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0]
Data0[9:5]
TXCLK_[0]
DDR Source Aligned Timing
(Nibble Order = 1 Default)
TXD_[4:0]
Data0[4:0]
Data0[9:5]
RXCLK_[0]
RXD_[4:0]
Data0[9:5]
Data0[4:0]
DDR Source Aligned Timing
(Nibble Order = 0)
TXCLK_[0]
TXD_[4:0]
Data0[9:5]
Data0[4:0]
RXCLK_[0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0]
Data0[9:5]
RXD_[4:0]
Data0[9:5]
Data0[4:0]
Figure 2-8. RTBI – Individual Channel Byte Ordering – Channel 0 Example
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