TLK3131_15 Datasheet, PDF (63/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SIGNAL
TDP0/TDN0
LOCATION
L4
L3
RDP0/RDN0
L8
L9
SIGNAL
VPP
TESTEN
AMUX1
AMUX0
LOCATION
A7
B7
J1
M10
M6
A9
RES[4:3,1]
C12
C3
GPI1
L12
K1
G10
GPO[4:0]
F10
G9
K2
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 3-5. Serial Side Data/Clock Pins
VOLTAGE
AVDD
AVDD
TYPE
CML Output
CML Input
DESCRIPTION
Transmit Differential Pairs High speed serial outputs. The data rate
of these signals is from 600 Mbps minimum to 3.75 Gbps maximum.
Receive Differential Pairs, High speed serial inputs with on-chip 100
Ω differential termination. Each input pair is terminated differentially
across an on chip 100 Ω resistor. The data rate of these signals is
from 600 Mbps minimum to 3.75 Gbps maximum.
Table 3-6. Miscellaneous Pins
VOLTAGE
DVDD
VDDO
N/A
N/A
N/A
VDDO
VDDO
TYPE
P
LVCMOS 2.5 V
Input
Analog Output
Analog Output
Resistive
Connection
LVCMOS 2.5 V
Input
LVCMOS 2.5 V
Output
DESCRIPTION
Efuse Controller Voltage (1.2 V). Must be tied to 1.2 V (DVDD) in the
system application.
Test Mode Enable Input – Must Be Grounded in the System
Application.
SERDES Analog Mux 1 RX – Must be Unconnected/Open in the
System Application
SERDES Analog Mux 0 TX – Must be Unconnected/Open in the
System Application
HSTL Impedance Control Resistors – 0.5% Tolerance Resistor
required of the following values:
150 Ohms between RES4 and GND
150 Ohms between RES3 and GND
50 Ohms between RES1 and GND
Note: These resistors cannot be shared between output pins.
General Purpose Input – Must be Grounded in the System
Application.
General Purpose Outputs – Must be Unconnected/Open in the
System Application.
It is recommended that these output ports go to headers or
non-populated resistor pads to facilitate probing of internal device
functions/settings during the initial system bring up process.
Also, to monitor PRBS testing real time, these outputs must be
available for probing on the application board.
Copyright © 2008–2009, Texas Instruments Incorporated
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Device Reset Requirements/Procedure
63