TLK3131_15 Datasheet, PDF (4/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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List of Figures
1-1 System Block Diagram – PCS.................................................................................................. 11
1-2 Block Diagram – TLK3131 Clocking Architecture............................................................................ 11
2-1 Single 10-Bit SERDES Application............................................................................................. 13
2-2 1000Base-X – Remote (Serial) Loopback Application ...................................................................... 13
2-3 1000Base-X – Local (Parallel ) Loopback Application ...................................................................... 13
2-4 TLK3131 Block Diagram ........................................................................................................ 14
2-5 Detailed 1000Base-X Core Block Diagram ................................................................................... 15
2-6 Block Diagram of SERDES Core............................................................................................... 15
2-7 RGMII – Individual Channel Byte Ordering – Channel 0 Example ........................................................ 17
2-8 RTBI – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 18
2-9 TBI – Individual Channel Byte Ordering – Channel 0 Example ............................................................ 19
2-10 GMII – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 20
2-11 EBI – Individual Channel Byte Ordering – Channel 0 Example............................................................ 21
2-12 REBI – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 22
2-13 NBI – Individual Channel Byte Ordering – Channel 0 Example............................................................ 23
2-14 RNBI – Individual Channel Byte Ordering – Channel 0 Example.......................................................... 24
2-15 TBID – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 25
2-16 NBID – Individual Channel Byte Ordering – Channel 0 Example.......................................................... 26
2-17 Receive Interface Timing – Source Centered/Aligned....................................................................... 27
2-18 Transmit Interface Timing ....................................................................................................... 28
2-19 Example High Speed I/O AC Coupled Mode ................................................................................. 29
2-20 Output Differential Voltage With 1-Tap FIR De-emphasis .................................................................. 29
2-21 CL22 – Management Interface Read Timing ................................................................................ 31
2-22 CL22 - Management Interface Write Timing.................................................................................. 31
2-23 CL22 – Indirect Address Method – Address Write........................................................................... 31
2-24 CL22 – Indirect Address Method – Data Write ............................................................................... 32
2-25 CL22 – Indirect Address Method – Address Write........................................................................... 32
2-26 CL22 – Indirect Address Method – Data Read .............................................................................. 32
3-1 Device Pinout Diagram – (Top View) .......................................................................................... 65
4-1 Transmit Output Waveform Parameter Definitions .......................................................................... 70
4-2 Transmit Template ............................................................................................................... 71
4-3 Receive Template ................................................................................................................ 71
4-4 Input Jitter ......................................................................................................................... 71
4-5 HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements ....................................... 73
4-6 HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements ......................................... 73
4-7 HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements ................................... 74
4-8 HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements................................... 74
4-9 HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements................................... 75
4-10 HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements..................................... 75
4-11 HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input Timing
Requirements ..................................................................................................................... 76
4-12 HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input Timing
Requirements ..................................................................................................................... 76
4-13 MDIO Read/Write Timing........................................................................................................ 77
4-14 JTAG Timing ...................................................................................................................... 78
4-15 HSTL I/O Schematic ............................................................................................................. 79
4-16 PACKAGE Information (Package Designator = ZWQ) ...................................................................... 80
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List of Figures
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