TLK3131_15 Datasheet, PDF (56/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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3.2 JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES
Use one of the following procedures to generate and verify the respective test patterns. It is assumed that
an appropriate external cable has been connected between serial outputs and serial inputs. No functional
parallel side connections are necessary.
• 1000Base-X Based High/Mixed/Low Frequency Test Pattern:
– Device Pin Setting(s):
• Ensure CODE primary input pin is low.
– Reset Device
• Issue a hard or soft reset (RST_N asserted for at least 10 us -or- Write 1’b1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used - Write 2’b01 to 37120.15:14
• If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Disable Comma Detection:
• Write 1’b0 to 17.7
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Issue Datapath Reset:
• Write 1’b1 to 16.11
• Write 1’b0, then 1’b1, followed by 1’b0 to 37636.14.
– Select Test Pattern:
• If High Frequency Pattern is desired:
– Write 3’b000 to 16.2:0
• If Low Frequency Pattern is desired:
– Write 3’b001 to 16.2:0
• If Mixed Frequency Pattern is desired:
– Write 3’b010 to 16.2:0
– Enable Test Pattern Generation:
• Write 1’b1 to 16.4
– Clear Counters:
• Read 22.15:0 and discard the value.
– Enable Test Pattern Verification:
• Write 1’b1 to 16.3
– Verify Test In Progress:
• Poll 21.1 asserted.
– The pattern verification is now in progress.
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 22.15:0, and verify 16’h0000 is read to confirm error free operation.
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Device Reset Requirements/Procedure
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