TLK3131_15 Datasheet, PDF (24/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
2.7.8 RNBI Mode (Reduced Nine Bit Interface)
Table 2-10. RNBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
Channel 0
TRANSMIT DATA 5 BITS
(INPUT)
TXD_[4:0]
RECEIVE DATA 5 BITS
(OUTPUT)
RXD_[4:0]
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
(Nibble Order = 1 Default)
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
(Nibble Order = 0)
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
RXD_[4:0]
TXCLK_[0]
TXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
DDR Source Aligned Timing
(Nibble Order = 1 Default)
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXCLK_[0]
RXD_[4:0]
TXCLK_[0]
TXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
DDR Source Aligned Timing
(Nibble Order = 0)
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
RXCLK_[0]
RXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
Figure 2-14. RNBI – Individual Channel Byte Ordering – Channel 0 Example
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