TLK3131_15 Datasheet, PDF (72/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 4-1. Parallel Interface – Valid Signal Operational Mode Definitions
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TIMING
MODE
NAME
USAGE MODE
RGMII, RTBI
1000Base-X Applications, Reduced Ten Bit Applications (RTBI)
Only DDR Timing Supported
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RGMII Mode
CH0: TX_EN/TX_ER = TXD_[4]
CH0: RX_DV/RX_ER = RXD_[4]
TBI, GMII
Ten Bit Interface Mode (TBI)
Only SDR Timing Supported
See Section 4.15: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.17: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In GMII Mode
CH0: TX_EN = TXC_[0]
CH0: TX_ER = TXC_[4]
CH0: RX_DV = RXC_[0]
CH0: RX_ER = RXC_[4]
Note: In TBI Mode
CH0: TX Data Bit 8 = TXC_[0]
CH0: TX Data Bit 9 = TXC_[4]
CH0: RX Data Bit 8 = RXC_[0]
CH0: RX Data Bit 9 = RXC_[4]
Eight Bit Interface Mode (EBI)
SDR Timing Support
EBI
See Section 4.15: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.17: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
REBI
Reduced Eight Bit Interface Mode (REBI)
DDR Timing Support
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Nine Bit Interface Mode (NBI)
(Un-encoded Data Byte + 1 Control Bit)
SDR Timing Support
See Section 4.15: HSTL Output Switching Characteristics (SDR Timing
NBI
Mode Only) and Section 4.17: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBI Mode
CH0: TX Control Bit = TXC_[0]
CH0: RX Control Bit = RXC_[0]
RNBI
Reduced Nine Bit Interface Mode (RNBI)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RNBI Mode
CH0: TX Control Bit = TXD_[4]
CH0: RX Control Bit = RXD_[4]
TBID
Ten Bit Interface DDR Mode (TBID)
Only DDR Timing Supported
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In TBID Mode
CH0: TX Data Bit 8 = TXC_[0]
CH0: TX Data Bit 9 = TXC_[4]
CH0: RX Data Bit 8 = RXC_[0]
CH0: RX Data Bit 9 = RXC_[4]
NBID
Nine Bit Interface DDR Mode (NBID)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.14: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.16: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBID Mode
CH0: TX Control Bit = TXC_[0]
CH0: RX Control Bit = RXC_[0]
TX SIGNALS USED
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
TXDATA = TXD_ [7:0]
TXCLK = TXCLK_ [0]
TXDATA = TXD_ [3:0]
TXCLK = TXCLK_ [0]
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
RX SIGNALS USED
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
RXDATA = RXD_ [7:0]
RXCLK = RXCLK_ [0]
RXDATA = RXD_ [3:0]
RXCLK = RXCLK_ [0]
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
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Electrical Specifications
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