TLK3131_15 Datasheet, PDF (30/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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Gigabit Ethernet, and FibreChannel 1 and 2. Register control gives selection between AC and DC
coupling at the receiver. When the receiver is AC coupled, the termination impedances of the receivers
are configured as 100 Ω with the center tap weakly tied to 0.8×VDDT with a capacitor to create an AC
ground. When the receiver is DC coupled, the common mode will be determined by both receiver and
transmitter characteristics.
The receive channel incorporates an adaptive equalizer. This circuit compensates for channel insertion
loss by amplifying the high frequency components of the signal, reducing inter-symbol interference.
Equalization can be enabled or disabled per register settings. Both the gain and bandwidth of the
equalizer are controlled by the receiver equalization logic. There are ten available equalization settings.
2.7.16 Loopback
Configuration for parallel or serial side loopback is possible.
An external loopback (requiring external connection) is also supported, which can be used with the PRBS
patterns, as well as the CRPAT, Mixed/High/Low Frequency tests.
2.7.17 Link Test Functions
The TLK3131 has an extensive suite of built in test functions to support system diagnostic requirements.
There is a built-in link test generator and verification logic. Several patterns can be selected via the MDIO
that offer extensive test coverage. The patterns are: 2⁷-1 or 2²³-1 PRBS (Pseudo Random Bit Stream),
CRPAT, high and low and mixed frequency patterns.
2.7.18 MDIO Management Interface
The TLK3131 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of
the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the
serial links. Normal operation of the TLK3131 is possible without use of this interface. However, some
additional features are accessible only through the MDIO.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device id and port address are determined by control pins (see Table 3-3).
TLK3131 will respond to MDIO accesses for two channels (channel 0 and channel 1), although there is no
datapath for channel 1.
In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2
individual channels (channel one datapath unusable) in TLK3131 are classified as 2 different ports. So for
any PRTAD[4:1] value there will be 2 ports per TLK3131.
TLK3131 will respond if the 4 MSB’s of PHY address field on MDIO protocol (PA[4:1]) matches
PRTAD[4:1]. The LSB of PHY address field (PA[0]) will determine which channel/port within TLK3131 to
respond to.
If PA[0] = 1b0, TLK3131 Channel 0 will respond.
If PA[0] = 1b1, TLK3131 Channel 1 will respond. (This channel does not have a datapath pinned out, and
is not usable).
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register will return a 0.
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