TLK3131_15 Datasheet, PDF (54/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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– Write 2’b11 to 36864.14:13 to set RX Loop Bandwidth
– Write 2’b11 to 36864.6:5 to set TX Loop Bandwidth
– Write 4’b0101 to 36864.11:8 to set MPY RX multiplier factor to 10
– Write 4’b0101 to 36864.3:0 to set MPY TX multiplier factor to 10
– Write 16’h4040 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
– Write 3'b000 to 37127.14:12 to set control bits for VCO tail current to 0
– Write 1’b1 to 37127.15 to enable Jitter Cleaner
– Wait 50 ms in order for JCPLL to lock
– If using clock bypass mode (JCPLL Off)
• JCPLL Mux Settings (see Figure 1-2)
– Select REFCLK input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
– If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select RXBYTE_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.13:12
– If Differential REFCLK used – Write 2’b11 to 37120.13:12
– Select SERDES TX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
– If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
– If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Select DELAY_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 37120.7:6
– If Differential REFCLK used – Write 2’b11 to 37120.7:6
– Select HSTL_2X_CLK (Default = Differential)
– Write 2b'01 to 4/5.37120.5:4 to select RX SERDES recovered clock as HSTL_2X_CLK
– Write 2’b00 to16.10:9 to select SERDES TX clock as RX_CLK output
– Write 7’h04 to 37121.6:0 to set HSTL_DIV2 to value of 4.
– Write 15’h1515 to 36864.14:0 SERDES_PLL_CONFIG to set MPY RX/TX multiplier factor to
10
– Write 16’h4040 to 36865 SERDES_RATE_CONFIG_TX_RX to set Half Rate
• Mode Control (see Table 2-2)
– Write 1’b0 to 17.0 for RX source centered mode
– Write 1’b0 to 17.1 for TX source centered mode
– Write 1’b1 to 17.2 to enable 8B/10B encode decode functions
– Write 1’b1 to 17.3 to enable 1000Base-X PCS TX & PCS RX functions
– Write 1’b1 to 17.4 to set nibble order, LSB on rising edge, MSB on falling edge
– Write 1’b1 to 17.5 to enable DDR data on TX/RX direction
– Write 1’b0 to 17.6 to disable FC_PH overlay detection
– Write 1’b1 to 17.7 to enable comma detection
– Write 1’b0 to 17.9 to disable full DDR mode
– Write 1’b0 to 16.8 to disable Farend Loop back
– Write 1’b0 to 0.14 to disable loop back mode
– Write 3’b111 to 36874.11:9 to set TX swing setting amplitude to 1375 mVdfpp
– Write 1’b1 to 36874.8 to set channel 0 TX CM bit
54
Device Reset Requirements/Procedure
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