TLK3131_15 Datasheet, PDF (85/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table A-6. Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01)
Nine/Ten Bit SERDES Mode – Clock Range Support (RATE[1:0]=01) (Half)
REFLK
Minimum
(MHz)
Maximum
(MHz)
Jitter Cleaner
Multiplier
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
SERDES PLL
Multiplier
Serial Data Rate (Mbps)
Half
Minimum
Maximum
200.0000
375.0000
OFF
200.0000
375.0000
5
1000.00
1875.00
100.0000
212.5000
OFF
100.0000
212.5000
10
1000.00
2125.00
50.0000
106.2500
OFF
50.0000
106.2500
20
1000.00
2125.00
0.25
5
0.25
10
200.0000
375.0000
0.25
50.0000
93.7500
20
1000.00
1875.00
0.5
5
200.0000
375.0000
0.5
100.0000
187.5000
10
1000.00
1875.00
100.0000
212.5000
0.5
50.0000
106.2500
20
1000.00
2125.00
1
5
100.0000
200.0000
1
100.0000
200.0000
10
1000.00
20000.00
50.0000
106.2500
1
50.0000
106.2500
20
1000.00
2125.00
2
5
50.0000
100.0000
2
100.0000
200.0000
10
1000.00
2000.00
2
20
Table A-7. Reference Clock Selection – 9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10)
Nine/Ten Bit SERDES Mode – Clock Range Support (RATE[1:0]=10) (Quarter)
REFLK
Minimum
(MHz)
Maximum
(MHz)
Jitter Cleaner
Multiplier
SERDES REFCLK
Minimum
(MHz)
Maximum
(MHz)
SERDES PLL
Multiplier
Serial Data Rate (Mbps)
Quarter
Minimum
Maximum
240.0000
375.0000
OFF
240.0000
375.0000
5
600.00
937.50
120.0000
212.5000
OFF
120.0000
212.5000
10
600.00
1062.50
60.0000
106.2500
OFF
60.0000
106.2500
20
600.00
1062.50
0.25
5
0.25
10
240.0000
375.0000
0.25
60.0000
93.7500
20
600.00
937.50
0.5
5
240.0000
375.0000
0.5
120.0000
187.5000
10
600.00
937.50
120.0000
212.5000
0.5
60.0000
106.2500
20
600.00
1062.50
1
5
120.0000
200.0000
1
120.0000
200.0000
10
600.00
1000.00
60.0000
106.2500
1
60.0000
106.2500
20
600.00
1062.50
2
5
60.0000
100.0000
2
120.0000
200.0000
10
600.00
1000.00
2
20
Copyright © 2008–2009, Texas Instruments Incorporated
APPENDIX A – Frequency Ranges Supported
85
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