TLK3131_15 Datasheet, PDF (20/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
2.7.4 GMII Mode (Gigabit Media Independent Interface)
Table 2-6. GMII – Lane To Functional Pin Mapping
DATA
CHANNEL
NUMBER
Channel 0
TX_EN
CONTROL
BIT
(INPUT)
TXC_[0]
TX_ER
CONTROL
BIT
(INPUT)
TXC_[4]
TRANSMIT
DATA BYTE
(INPUT)
TXD_[7:0]
RX_DV
CONTROL
BIT
(OUTPUT)
RXC_[0]
RX_ER
RECEIVE
CONTROL BIT DATA BYTE
(OUTPUT) (OUTPUT)
RXC_[4]
RXD_[7:0]
TRANSMIT
CLOCK
(INPUT)
TXCLK_[0]
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[0]
TXCLK_[0]
SDR Rising Edge Aligned Timing
TXC_[0],TXC_[4],TXD_[7:0]
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
TXCLK_[0]
TXC_[0],TXC_[4],TXD_[7:0]
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
SDR Falling Edge Aligned Timing
{TX_EN,TX_ER,Data0[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
RXCLK_[0]
RXC_[0],RXC_[4],RXD_[7:0]
{RX_DV,RX_ER,Data0[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
Figure 2-10. GMII – Individual Channel Byte Ordering – Channel 0 Example
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