TLK3131_15 Datasheet, PDF (22/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
2.7.6 REBI Mode (Reduced Eight Bit Interface)
Table 2-8. REBI – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
Channel 0
TRANSMIT DATA 4 BITS
(INPUT)
TXD_[3:0]
RECEIVE DATA 4 BITS
(OUTPUT)
RXD_[3:0]
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
TXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 1 Default)
TXCLK_[0]
DDR Source Centered Timing
(Nibble Order = 0)
TXD_[3:0]
Data0[3:0]
Data0[7:4]
TXD_[3:0]
Data0[7:4]
Data0[3:0]
RXCLK_[0]
RXD_[3:0]
TXCLK_[0]
TXD_[3:0]
Data0[3:0]
Data0[7:4]
DDR Source Aligned Timing
(Nibble Order = 1 Default)
Data0[3:0]
Data0[7:4]
RXCLK_[0]
RXD_[3:0]
Data0[7:4]
Data0[3:0]
TXCLK_[0]
TXD_[3:0]
DDR Source Aligned Timing
(Nibble Order = 0)
Data0[7:4]
Data0[3:0]
RXCLK_[0]
RXCLK_[0]
RXD_[3:0]
Data0[3:0]
Data0[7:4]
RXD_[3:0]
Data0[7:4]
Data0[3:0]
Figure 2-12. REBI – Individual Channel Byte Ordering – Channel 0 Example
22
Detailed Description
Submit Documentation Feedback
Product Folder Link(s): TLK3131
Copyright © 2008–2009, Texas Instruments Incorporated