TLK3131_15 Datasheet, PDF (38/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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Table 2-31. PHY_EXT_ADDRESS_DATA
BIT(s)
31.15:0
ADDRESS: 0x1F
DEFAULT: 0x0000
NAME
DESCRIPTION
Ext address data
register
This register contains the data associated with the register address written in Register
30 (0x1E)
ACCESS
RW
2.9 Top Level Programmers Reference
Following registers can be addressed indirectly through Clause 22.
Table 2-32. SERDES_PLL_CONFIG
BIT(s)
36864.14:13
36864. 12
36864.11:8
36864.7
36864.6:5
36864.4
36864. 3:0
ADDRESS: 0x9000
DEFAULT: 0x1515
NAME
DESCRIPTION
Loop Bandwidth
RX(LB_RX)
SERDES RX PLL Bandwidth settings
00 = Applicable when JC PLL is not engaged
01 = Reserved
10 = Reserved
11 = Applicable when JC PLL is engaged
ENPLL_RX
0 = Disables PLL in SERDES RX
1 = Enable PLL in SERDES RX
PLL Multiplier factor RX SERDES RX PLL multiplier setting
(MPY_RX)
See Table 2-33
BUSWIDTH
1 = 8 bit mode. Applicable for only EBI and REBI modes
0 = 10 Bit mode. Applicable for all other modes
Loop Bandwidth TX
(LB_TX)
SERDES TX PLL Bandwidth settings
00 = Applicable when JC PLL is not engaged
01 = Reserved
10 = Reserved
11 = Applicable when JC PLL is engaged
ENPLL_TX
0 = Disables PLL in SERDES TX
1 = Enable PLL in SERDES TX
PLL Multiplier factor TX SERDES TX PLL multiplier setting
(MPY_TX)
See Table 2-33
ACCESS
RW
RW
RW
RW
RW
RW
RW
Table 2-33. PLL Multiplier Control
36864[11:8]/ 36864[3:0]
VALUE
PLL MULTIPLIER FACTOR
0000
4x
0001
5x
0010
6x
0011
Reserved
0100
8x
0101
10x
0110
12x
0111
12.5x
VALUE
1000
1001
1010
1011
1100
1101
1110
1111
36864[11:8]/ 36864[3:0]
PLL MULTIPLIER FACTOR
15x
20x
25x
Reserved
Reserved
50x
60x
Reserved
38
Detailed Description
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