TLK3131_15 Datasheet, PDF (53/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
3 Device Reset Requirements/Procedure
3.1 Gigabit Ethernet Mode (RGMII)
Power down sequence for channel 1
Note: Common for all modes after device reset⁽¹⁾
• Write 1’b0 to 36868.0 to disable receiver for unused channel
• Write 1’b0 to 36876.0 to disable transmitter for unused channel
• Set LSB of PHY address to 1
• Write 1’b1 to 0.11 to power down unused channel
• Set LSB of PHY address to 0
REFCLK frequency = 125 MHz, Serdes Data Rate = Half Rate, Mode = Transceiver, Edge Mode = Source
Centered Mode, RX_CLK[n] out = TXBCLK[n], Jitter Cleaner PLL Multiplier Ratio = 1X or Off
• Device Pin Setting(s) – Pin settings allow for maximum software configurability.
– Ensure CODE input pin is Low.
– Ensure PLOOP input pin is Low.
– Ensure SLOOP input pin is Low.
– Ensure SPEED [1:0] input pins are both High.
– Ensure ENABLE input pin is High.
– Ensure PRBS_EN input pin is Low.
• Reset Device
– Issue a hard or soft reset (RST_N asserted for at least 10 μs -or- Write 1’b1 to 0.15)
• Power Down Sequence Note: This step is mandatory for proper functionality
– Refer to Power down sequence above
• Clock Configuration
– If using JCPLL (JCPLL 1X)
• JCPLL Mux Settings (see Figure 1-2)
– Select REFCLK input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
– If Differential REFCLK used – Write 2’b00 to 37120.15:14
• Write 2’b11 to 37120.13:12 to select differential REFCLKP/N as RXBYTECLK
• Write 4’b0000 to 37120.11:8 to select jitter cleaned clock for SERDES TX/RX.
• Write 2’b11 to 37120.7:6 to select differential REFCLKP/N as delay stopwatch clock input
• Write 2’b00 to 37120.5:4 to select jitter cleaned clock for HSTL VTP 2x
• Write 2’b00 to 16.10:9 to select SERDES TX clock as RX_CLK output
• Write 16’h0081 to 37126 to set Charge pump control
• Write 16’h00A0 to 37128 to set TXRX output divider
• Clock Divide Settings (see Figure A-1)
– Write 7’b1000000 to 37124.14:8 to set REF_DIV to value of 1
– Write 1’b1 to 37124.15 REFDIV_EN to enable reference clock divider
– Write 7’h18 to 37124.6:0 to set FB_DIV to value of 24
– Write 1’b1 to 37124.7 FBDIV_EN to enable feedback divider
– Write 7’h18 to 37125.6:0 to set RXTX_DIV to value of 24
– Write 1’b1 to 37125.7 OUTDIV_EN to enable RXTX_DIV output divider
– Write 7’h0D to 37121.14:8 to set HSTL_DIV to value of 13
– Write 7’h06 to 37121.6:0 to set HSTL_DIV2 to value of 6
(1) Note: All global registers must be accessed indirectly through Clause 22.
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Device Reset Requirements/Procedure
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