TLK3131_15 Datasheet, PDF (74/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
4.15 HSTL Output Switching Characteristics (SDR Timing Mode Only)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
T_duty
t_period
T_freq
T_pd
T_pd
RXCLK Duty Cycle
RXCLK Period
Rising and Falling Edge Aligned Data
Note: C_load = 10pF, using timing reference of VDDQ/2.
Rising and Falling Edge Aligned Data
RXCLK Frequency
Rising and Falling Edge Aligned Data
RXCLK rising to RXDATA valid.
RXCLK falling to RXDATA valid.
Rising Edge Aligned, See Figure 4-7
Note: C_load = 10pF, using timing reference of VDDQ/2.
Falling Edge Aligned, See Figure 4-8
Note: C_load = 10pF, using timing reference of VDDQ/2.
t_PERIOD
RXCLK
T_PD
V_OH(ac)
RXDATA VDDQ/2
V_OL(ac)
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MIN
40%
2.67
60
–0.10 ×
t_period
–0.10 ×
t_period
MAX UNIT
60%
16.67
375
+0.10 ×
t_period
+0.10 ×
t_period
ns
MHz
ps
ps
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-7. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements
RXCLK
t_PERIOD
T_PD
V_OH(ac)
RXDATA VDDQ/2
V_OL(ac)
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-8. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements
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Electrical Specifications
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