TLK3131_15 Datasheet, PDF (78/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
4.19 JTAG Timing Requirements Over Recommended Operating Conditions
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
t_period
t_setup
t_hold
T_valid
TCK period
TDI/TMS/TRST_N setup to ↑ TCK
TDI/TMS/TRST_N hold from ↑ TCK
TDO delay from TCK falling
See Figure 4-14.
See Figure 4-14.
See Figure 4-14.
See Figure 4-14.
66.67
3
5
0
MAX
5
UNIT
ns
ns
ns
ns
TCK
TDI/TMS/
TRST_N
t_PERIOD
t_SETUP
t_HOLD
t_VALID
TDO
Figure 4-14. JTAG Timing
50 W
OUTPUT
VDDQ
50 W transmission line
VDDQ
150/200/
300/Open
(W)
+
150/200/
300/Open
(W)
GND
-
RW
VREF
RW
GND
PCB
Figure 4-15. HSTL I/O Schematic
INPUT
78
Electrical Specifications
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