TLK3131_15 Datasheet, PDF (76/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
4.17 HSTL (SDR Timing Mode Only) Input Timing Requirements
PARAMETER
TEST CONDITIONS
t_setup
TXDATA setup prior to TXCLK
transition high
Falling Edge Aligned (Rising Edge Sampled) Data See
Figure 4-11.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
t_hold TXDATA hold after TXCLK
transition high
Falling Edge Aligned (Rising Edge Sampled) Data See
Figure 4-11.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
t_setup
TXDATA setup prior to TXCLK
transition low
Rising Edge Aligned (Falling Edge Sampled) Data See
Figure 4-12.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
t_hold TXDATA hold after TXCLK
transition low
Rising Edge Aligned (Falling Edge Sampled) Data See
Figure 4-12.
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
t_duty TXCLK Duty Cycle
Rising and Falling Edge Sampled Data
Note: Input timing reference of VDDQ/2, with ±1 ns/V rise
time on all input signals.
t_period TXCLK Period
T_freq TXCLK Frequency
Rising and Falling Edge Aligned Data
Rising and Falling Edge Aligned Data
(1) All typical values are at 25°C and with a nominal supply.
tPERIOD
TXCLK
TXDATA
VIH(ac)
VDDQ/2
VIL(ac)
tSETUP
tHOLD
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MIN NOM⁽¹⁾ MAX UNIT
480
ps
480
ps
480
ps
480
ps
40%
2.67
60
60%
16.67 ns
375 MHz
VIH(ac)
VDDQ/2
VIL(ac)
Figure 4-11. HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input
Timing Requirements
TXCLK
V_IH(ac)
TXDATA VDDQ/2
V_IL(ac)
t_PERIOD
t_SETUP
t_HOLD
V_IH(ac)
VDDQ/2
V_IL(ac)
Figure 4-12. HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input
Timing Requirements
76
Electrical Specifications
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