TLK3131_15 Datasheet, PDF (3/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
4.5 SINGLE ENDED REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLK) ...................... 67
4.6 JITTER CLEANER TIMING PARAMETERS ........................................................................... 67
4.7 LVCMOS ELECTRICAL CHARACTERISTICS ........................................................................ 67
4.8 MDIO ELECTRICAL CHARACTERISTICS ............................................................................ 68
4.9 HSTL SIGNALS (VDDQ = 1.5/1.8 V) ................................................................................... 68
4.10 SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS ......................................................... 68
4.11 DRIVER TEMPLATE PARAMETERS .................................................................................. 70
4.12 TIMING DEFINITION ..................................................................................................... 70
4.13 APPLICATION MODES .................................................................................................. 71
4.14 HSTL Output Switching Characteristics (DDR Timing Mode Only) ................................................. 73
4.15 HSTL Output Switching Characteristics (SDR Timing Mode Only) ................................................. 74
4.16 HSTL (DDR Timing Mode Only) Input Timing Requirements ....................................................... 75
4.17 HSTL (SDR Timing Mode Only) Input Timing Requirements ........................................................ 76
4.18 MDIO Timing Requirements Over Recommended Operating Conditions ......................................... 77
4.19 JTAG Timing Requirements Over Recommended Operating Conditions .......................................... 78
4.20 PACKAGE DISSIPATION RATING ..................................................................................... 81
A APPENDIX A – Frequency Ranges Supported ....................................................................... 82
A.1 Recovered Byte Clock Jitter Cleaner Mode: ........................................................................... 95
B APPENDIX B – Jitter Cleaner PLL External Loop Filter ........................................................... 97
C APPENDIX C – Device Test Mode ........................................................................................ 98
Revision History ......................................................................................................................... 98
Copyright © 2008–2009, Texas Instruments Incorporated
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