TLK3131_15 Datasheet, PDF (26/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
2.7.10 NBID Mode (Nine Bit Interface DDR)
Table 2-12. NBID – Lane To Functional Pin Mapping
DATA CHANNEL
NUMBER
Channel 0
TRANSMIT DATA 9 BITS
(INPUT)
{TXC_[0],TXD_[7:0]}
RECEIVE DATA 9 BITS
(OUTPUT)
{RXC_[0],RXD_[7:0]}
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[0]
DDR Source Centered Timing
TXC_[0], TXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
www.ti.com
RECEIVE CLOCK
(OUTPUT)
RXCLK_ [0]
RXCLK_[0]
RXC_[0], RXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
TXCLK_[0]
TXC_[0], TXD_[7:0]
DDR Source Aligned Timing
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
RXCLK_[0]
RXC_[0], RXD_[7:0]
Data0[8:0] = {Control
Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte}
Figure 2-16. NBID – Individual Channel Byte Ordering – Channel 0 Example
26
Detailed Description
Submit Documentation Feedback
Product Folder Link(s): TLK3131
Copyright © 2008–2009, Texas Instruments Incorporated